The evolution of integrated circuit designs has resulted in higher operating frequency, increased numbers of transistors, and physically smaller devices. This continuing trend has generated ever-increasing area densities of integrated circuits. To further increase possible densities of integrated circuits, it may be desirable in some instances to electrically couple an active circuit layer on a die to another active circuit layer on the same, or a different, die by means of an electrically conductive through silicon via. A typical through silicon via may simply be a void within a bulk silicon portion of a die filled with a bulk material of approximately uniform composition, for example an alloy of copper.
Many materials may undergo a physical expansion or contraction resulting from a change in temperature. A coefficient of thermal expansion (CTE) may represent a change in unit volume of a bulk material for a unit change in temperature. If a volume of a first bulk material encloses a second volume of a second bulk material with different coefficient of thermal expansion from the first bulk material with zero stress at a given temperature, a change in temperature may cause a non-zero stress to develop at an interface of the different bulk materials. In some cases, under a sufficient change in temperature, or a sufficient number of temperature excursion cycles, a stress at an interface of the different bulk materials may exceed a certain critical stress and cause a permanent deformation or dislocation in one or the other or both bulk materials. Alternatively, performance of the integrated circuit device may degrade from an increased stress at an interface of different bulk materials, without either material undergoing a permanent deformation or dislocation.
During a normal manufacturing cycle, packages containing integrated circuits may undergo various processes, some of which may occur at an elevated temperature. For example, a package containing integrated circuits may undergo, for example, a solder reflow process, after perhaps being at room temperature. In a solder reflow process, various components within the package, including the integrated circuits and accompanying bulk silicon to which the integrated circuits may be coupled may approach, or even exceed a temperature at which a solder reflows, e.g., perhaps 230° C. for a representative Pb-free solder, contrasting with a normal storage temperature, for example, perhaps 25° C. In the present example, a package and its components may undergo a significant temperature change, e.g. based on the present example, as much or greater than 205° C.
Further, under normal operation, integrated circuits such as processors generate heat that may cause various components within a package, including the integrated circuits and accompanying bulk silicon to which the integrated circuits may be coupled, to undergo temperature variations. While temperature excursions under normal operation may not be as extreme as those experienced in a manufacturing process, throughout a product's design life, a package and its components including the integrated circuits and accompanying bulk silicon to which the integrated circuits may be coupled may undergo a high number of temperature excursions resulting from normal operation.
Copper has a bulk linear CTE of approximately 16.5 ppm/° C. in contrast to silicon, which has a bulk linear CTE of approximately 2.6 ppm/° C. Thus, a unit volume of copper expands considerably more than a unit volume of silicon. Because a typical through silicon via may simply be a void in a bulk silicon portion of an integrated circuit die filled with an alloy of copper and the CTE of each material is almost an order of magnitude different, a mechanical stress may be induced at a copper—silicon interface when the package undergoes a temperature excursion.
For example, FIG. 1(a) represents a group of prior art through silicon vias, showing a portion of a bulk silicon die with integrated circuits 100. Prior art through silicon vias 112 may be electrically coupled to metal pads 108 through an electrically conductive seed layer 114. Between an electrically conductive seed layer 114 and a portion of the bulk silicon die 102 may be a passivation or electrical insulation layer 116. Metal pads 108 and a portion of the bulk silicon die 102 may be separated by an interlayer dielectric (ILD) material 104. A layer of ILD 104 coupled to a portion of the bulk silicon die 102 between metal pads 108 may underlie a layer of passivation material 110 or a protection layer 106. FIG. 1(b) and FIG. 1(c) represent a prior art through silicon via suffering stress induced, mechanical failures of delamination 120 and die cracking 118, respectively. A prior art through silicon via may have a bulk CTE substantially similar in magnitude to the bulk CTE of the continuous metal phase and substantially different from the bulk CTE of silicon, leading to significant principal stresses under temperature excursions. The significant principal stresses in turn may cause mechanical failures of the integrated circuit such as delamination 120 or die cracking 118. Further, significant principal stresses, without causing delamination 120 or die cracking 118 may cause degraded performance within an integrated circuit.
To maintain a mechanical stress resulting from a CTE mismatch below a critical stress of either bulk material for a given temperature excursion, via size may be reduced, spacing between adjacent vias may be increased, or vias may be positioned far from active circuitry. Each of these solution options may lead to increased die size, lower density circuits than may otherwise be realized or increased cost per die.